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<div class="header">
  <div class="summary">
<a href="#enum-members">Enumerations</a> &#124;
<a href="#func-members">Functions</a>  </div>
  <div class="headertitle">
<div class="title">SRC: System Reset Controller Driver</div>  </div>
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<div class="contents">
<a name="details" id="details"></a><h2 class="groupheader">Overview</h2>
<p>The MCUXpresso SDK provides a peripheral driver for the System Reset Controller (SRC) module.</p>
<p>The System Reset Controller (SRC) controls the reset and boot operation of the SoC. It is responsible for the generation of all reset signals and boot decoding. The reset controller determines the source and the type of reset, such as POR, WARM, COLD, and performs the necessary reset qualification and stretching sequences. Based on the type of reset, the reset logic generates the reset sequence for the entire IC. </p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="enum-members"></a>
Enumerations</h2></td></tr>
<tr class="memitem:gaf647f7dbfbed8b1612675ab132cfa244"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__src.html#gaf647f7dbfbed8b1612675ab132cfa244">_src_reset_status_flags</a> { <br/>
&#160;&#160;<a class="el" href="group__src.html#ggaf647f7dbfbed8b1612675ab132cfa244a1ec8e8b05164a48af564b20d8a3f667a">kSRC_WarmBootIndicationFlag</a> = SRC_SRSR_WBI_MASK, 
<br/>
&#160;&#160;<a class="el" href="group__src.html#ggaf647f7dbfbed8b1612675ab132cfa244a35d666ccd943a593bc1af289e6233adb">kSRC_TemperatureSensorResetFlag</a> = SRC_SRSR_TSR_MASK, 
<br/>
&#160;&#160;<a class="el" href="group__src.html#ggaf647f7dbfbed8b1612675ab132cfa244a0cfd86a5b8b7110fac02e1304d33d218">kSRC_Wdog3ResetFlag</a> = SRC_SRSR_WDOG3_RST_B_MASK, 
<br/>
&#160;&#160;<a class="el" href="group__src.html#ggaf647f7dbfbed8b1612675ab132cfa244abc557d5e2e199f9727744af4b181602b">kSRC_JTAGSoftwareResetFlag</a> = SRC_SRSR_SJC_MASK, 
<br/>
&#160;&#160;<a class="el" href="group__src.html#ggaf647f7dbfbed8b1612675ab132cfa244a8a43d19a82614c4c1d571dad1f492628">kSRC_JTAGGeneratedResetFlag</a> = SRC_SRSR_JTAG_MASK, 
<br/>
&#160;&#160;<a class="el" href="group__src.html#ggaf647f7dbfbed8b1612675ab132cfa244abce52ce03031bdb1b0d76576daf418df">kSRC_WatchdogResetFlag</a> = SRC_SRSR_WDOG_MASK, 
<br/>
&#160;&#160;<a class="el" href="group__src.html#ggaf647f7dbfbed8b1612675ab132cfa244af8e87b67801dd22376d5b284722d02e3">kSRC_IppUserResetFlag</a> = SRC_SRSR_IPP_USER_RESET_B_MASK, 
<br/>
&#160;&#160;<a class="el" href="group__src.html#ggaf647f7dbfbed8b1612675ab132cfa244a3008203f1efa3b9385545f53445844fb">kSRC_CsuResetFlag</a> = SRC_SRSR_CSU_RESET_B_MASK, 
<br/>
&#160;&#160;<a class="el" href="group__src.html#ggaf647f7dbfbed8b1612675ab132cfa244af7eba139e63dffc69983a262551a8856">kSRC_IppResetPinFlag</a> = SRC_SRSR_IPP_RESET_B_MASK
<br/>
 }</td></tr>
<tr class="memdesc:gaf647f7dbfbed8b1612675ab132cfa244"><td class="mdescLeft">&#160;</td><td class="mdescRight">SRC reset status flags.  <a href="group__src.html#gaf647f7dbfbed8b1612675ab132cfa244">More...</a><br/></td></tr>
<tr class="separator:gaf647f7dbfbed8b1612675ab132cfa244"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga95d1580a5ef39f6d3a5152a1be58e1ba"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__src.html#ga95d1580a5ef39f6d3a5152a1be58e1ba">_src_status_flags</a> { <a class="el" href="group__src.html#gga95d1580a5ef39f6d3a5152a1be58e1baa53addfa0a919d77cdfa12c3c6114e88f">kSRC_Core0WdogResetReqFlag</a>
 }</td></tr>
<tr class="memdesc:ga95d1580a5ef39f6d3a5152a1be58e1ba"><td class="mdescLeft">&#160;</td><td class="mdescRight">SRC interrupt status flag.  <a href="group__src.html#ga95d1580a5ef39f6d3a5152a1be58e1ba">More...</a><br/></td></tr>
<tr class="separator:ga95d1580a5ef39f6d3a5152a1be58e1ba"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac64aa4121e8d426a94f0826bbd7d49ac"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__src.html#gac64aa4121e8d426a94f0826bbd7d49ac">src_mix_reset_stretch_cycles_t</a> { <br/>
&#160;&#160;<a class="el" href="group__src.html#ggac64aa4121e8d426a94f0826bbd7d49acaa217f0915ef6135677b3a91fc79331f0">kSRC_MixResetStretchCycleAlt0</a> = 0U, 
<br/>
&#160;&#160;<a class="el" href="group__src.html#ggac64aa4121e8d426a94f0826bbd7d49aca08bea4f6078f98076d09164fb79a24fe">kSRC_MixResetStretchCycleAlt1</a> = 1U, 
<br/>
&#160;&#160;<a class="el" href="group__src.html#ggac64aa4121e8d426a94f0826bbd7d49aca523d03fc789c467d88fe744cb4aafd44">kSRC_MixResetStretchCycleAlt2</a> = 2U, 
<br/>
&#160;&#160;<a class="el" href="group__src.html#ggac64aa4121e8d426a94f0826bbd7d49acae0e765d1cd3898d811c441c5da436c9c">kSRC_MixResetStretchCycleAlt3</a> = 3U
<br/>
 }</td></tr>
<tr class="memdesc:gac64aa4121e8d426a94f0826bbd7d49ac"><td class="mdescLeft">&#160;</td><td class="mdescRight">Selection of SoC mix power reset stretch.  <a href="group__src.html#gac64aa4121e8d426a94f0826bbd7d49ac">More...</a><br/></td></tr>
<tr class="separator:gac64aa4121e8d426a94f0826bbd7d49ac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga24d2539758a32392b0d25f46a9f90b4e"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__src.html#ga24d2539758a32392b0d25f46a9f90b4e">src_wdog3_reset_option_t</a> { <br/>
&#160;&#160;<a class="el" href="group__src.html#gga24d2539758a32392b0d25f46a9f90b4eafb2fea029e1f79976dd556e130e2fbca">kSRC_Wdog3ResetOptionAlt0</a> = 0U, 
<br/>
&#160;&#160;<a class="el" href="group__src.html#gga24d2539758a32392b0d25f46a9f90b4ea93e0c56b34582af6b2713feda778912e">kSRC_Wdog3ResetOptionAlt1</a> = 1U
<br/>
 }</td></tr>
<tr class="memdesc:ga24d2539758a32392b0d25f46a9f90b4e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Selection of WDOG3 reset option.  <a href="group__src.html#ga24d2539758a32392b0d25f46a9f90b4e">More...</a><br/></td></tr>
<tr class="separator:ga24d2539758a32392b0d25f46a9f90b4e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5b40161d6cf7c90a651afd9047b6bedd"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__src.html#ga5b40161d6cf7c90a651afd9047b6bedd">src_warm_reset_bypass_count_t</a> { <br/>
&#160;&#160;<a class="el" href="group__src.html#gga5b40161d6cf7c90a651afd9047b6beddae2e8afc71fab41ccbac78e6a8d69ff62">kSRC_WarmResetWaitAlways</a> = 0U, 
<br/>
&#160;&#160;<a class="el" href="group__src.html#gga5b40161d6cf7c90a651afd9047b6beddad20bc2e2d97c95046d65940f111e9584">kSRC_WarmResetWaitClk16</a> = 1U, 
<br/>
&#160;&#160;<a class="el" href="group__src.html#gga5b40161d6cf7c90a651afd9047b6bedda8c3d2f6cd0c0f36da9a342e3c3eb77f8">kSRC_WarmResetWaitClk32</a> = 2U, 
<br/>
&#160;&#160;<a class="el" href="group__src.html#gga5b40161d6cf7c90a651afd9047b6bedda5bbedec3e30404b252af1b02af0042c0">kSRC_WarmResetWaitClk64</a> = 3U
<br/>
 }</td></tr>
<tr class="memdesc:ga5b40161d6cf7c90a651afd9047b6bedd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Selection of WARM reset bypass count.  <a href="group__src.html#ga5b40161d6cf7c90a651afd9047b6bedd">More...</a><br/></td></tr>
<tr class="separator:ga5b40161d6cf7c90a651afd9047b6bedd"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:ga1acc402410430b368530084805b022ac"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__src.html#ga1acc402410430b368530084805b022ac">SRC_EnableWDOG3Reset</a> (SRC_Type *base, bool enable)</td></tr>
<tr class="memdesc:ga1acc402410430b368530084805b022ac"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable the WDOG3 reset.  <a href="#ga1acc402410430b368530084805b022ac">More...</a><br/></td></tr>
<tr class="separator:ga1acc402410430b368530084805b022ac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8d6fe5d7299234c1611e62e697b9ed7c"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__src.html#ga8d6fe5d7299234c1611e62e697b9ed7c">SRC_SetMixResetStretchCycles</a> (SRC_Type *base, <a class="el" href="group__src.html#gac64aa4121e8d426a94f0826bbd7d49ac">src_mix_reset_stretch_cycles_t</a> option)</td></tr>
<tr class="memdesc:ga8d6fe5d7299234c1611e62e697b9ed7c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the mix power up reset stretch mix reset width.  <a href="#ga8d6fe5d7299234c1611e62e697b9ed7c">More...</a><br/></td></tr>
<tr class="separator:ga8d6fe5d7299234c1611e62e697b9ed7c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa00efe244ad4bf9f2b2fbf434adba463"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__src.html#gaa00efe244ad4bf9f2b2fbf434adba463">SRC_EnableCoreDebugResetAfterPowerGate</a> (SRC_Type *base, bool enable)</td></tr>
<tr class="memdesc:gaa00efe244ad4bf9f2b2fbf434adba463"><td class="mdescLeft">&#160;</td><td class="mdescRight">Debug reset would be asserted after power gating event.  <a href="#gaa00efe244ad4bf9f2b2fbf434adba463">More...</a><br/></td></tr>
<tr class="separator:gaa00efe244ad4bf9f2b2fbf434adba463"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga466bed6430d969bf3dc0e75e7d7d41eb"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__src.html#ga466bed6430d969bf3dc0e75e7d7d41eb">SRC_SetWdog3ResetOption</a> (SRC_Type *base, <a class="el" href="group__src.html#ga24d2539758a32392b0d25f46a9f90b4e">src_wdog3_reset_option_t</a> option)</td></tr>
<tr class="memdesc:ga466bed6430d969bf3dc0e75e7d7d41eb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the Wdog3_rst_b option.  <a href="#ga466bed6430d969bf3dc0e75e7d7d41eb">More...</a><br/></td></tr>
<tr class="separator:ga466bed6430d969bf3dc0e75e7d7d41eb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacac05ee697093204afccc4247bab1161"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__src.html#gacac05ee697093204afccc4247bab1161">SRC_DoSoftwareResetARMCoreDebug</a> (SRC_Type *base)</td></tr>
<tr class="memdesc:gacac05ee697093204afccc4247bab1161"><td class="mdescLeft">&#160;</td><td class="mdescRight">Software reset for debug of arm platform only.  <a href="#gacac05ee697093204afccc4247bab1161">More...</a><br/></td></tr>
<tr class="separator:gacac05ee697093204afccc4247bab1161"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafb053b235cafaec161ab7772dd34c2c9"><td class="memItemLeft" align="right" valign="top">static bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__src.html#gafb053b235cafaec161ab7772dd34c2c9">SRC_GetSoftwareResetARMCoreDebugDone</a> (SRC_Type *base)</td></tr>
<tr class="memdesc:gafb053b235cafaec161ab7772dd34c2c9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Check if the software reset for debug of arm platform only is done.  <a href="#gafb053b235cafaec161ab7772dd34c2c9">More...</a><br/></td></tr>
<tr class="separator:gafb053b235cafaec161ab7772dd34c2c9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga720bd353336716e97c2ed486f3f972e9"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__src.html#ga720bd353336716e97c2ed486f3f972e9">SRC_DoSoftwareResetARMCore0</a> (SRC_Type *base)</td></tr>
<tr class="memdesc:ga720bd353336716e97c2ed486f3f972e9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Do software reset the ARM core0 only.  <a href="#ga720bd353336716e97c2ed486f3f972e9">More...</a><br/></td></tr>
<tr class="separator:ga720bd353336716e97c2ed486f3f972e9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0893922f62b39cf97053d6909d2b6721"><td class="memItemLeft" align="right" valign="top">static bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__src.html#ga0893922f62b39cf97053d6909d2b6721">SRC_GetSoftwareResetARMCore0Done</a> (SRC_Type *base)</td></tr>
<tr class="memdesc:ga0893922f62b39cf97053d6909d2b6721"><td class="mdescLeft">&#160;</td><td class="mdescRight">Check if the software for ARM core0 is done.  <a href="#ga0893922f62b39cf97053d6909d2b6721">More...</a><br/></td></tr>
<tr class="separator:ga0893922f62b39cf97053d6909d2b6721"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacfc6bc3b452aa65c3da86e45ea7be3b6"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__src.html#gacfc6bc3b452aa65c3da86e45ea7be3b6">SRC_AssertEIMReset</a> (SRC_Type *base, bool enable)</td></tr>
<tr class="memdesc:gacfc6bc3b452aa65c3da86e45ea7be3b6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Assert the EIM reset.  <a href="#gacfc6bc3b452aa65c3da86e45ea7be3b6">More...</a><br/></td></tr>
<tr class="separator:gacfc6bc3b452aa65c3da86e45ea7be3b6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac96321bdff82d5abc821d061323447df"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__src.html#gac96321bdff82d5abc821d061323447df">SRC_EnableWDOGReset</a> (SRC_Type *base, bool enable)</td></tr>
<tr class="memdesc:gac96321bdff82d5abc821d061323447df"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable the WDOG Reset in SRC.  <a href="#gac96321bdff82d5abc821d061323447df">More...</a><br/></td></tr>
<tr class="separator:gac96321bdff82d5abc821d061323447df"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga855481246b5b5a4227d7d04f034ceaaa"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__src.html#ga855481246b5b5a4227d7d04f034ceaaa">SRC_SetWarmResetBypassCount</a> (SRC_Type *base, <a class="el" href="group__src.html#ga5b40161d6cf7c90a651afd9047b6bedd">src_warm_reset_bypass_count_t</a> option)</td></tr>
<tr class="memdesc:ga855481246b5b5a4227d7d04f034ceaaa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the delay count of waiting MMDC's acknowledge.  <a href="#ga855481246b5b5a4227d7d04f034ceaaa">More...</a><br/></td></tr>
<tr class="separator:ga855481246b5b5a4227d7d04f034ceaaa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga627a1af6de292a91078ce42a1d8976e6"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__src.html#ga627a1af6de292a91078ce42a1d8976e6">SRC_EnableWarmReset</a> (SRC_Type *base, bool enable)</td></tr>
<tr class="memdesc:ga627a1af6de292a91078ce42a1d8976e6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable the WARM reset.  <a href="#ga627a1af6de292a91078ce42a1d8976e6">More...</a><br/></td></tr>
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<tr class="memitem:ga0d5ef0414e918346bb20bf5715d8cfea"><td class="memItemLeft" align="right" valign="top">static uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__src.html#ga0d5ef0414e918346bb20bf5715d8cfea">SRC_GetStatusFlags</a> (SRC_Type *base)</td></tr>
<tr class="memdesc:ga0d5ef0414e918346bb20bf5715d8cfea"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get interrupt status flags.  <a href="#ga0d5ef0414e918346bb20bf5715d8cfea">More...</a><br/></td></tr>
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<tr class="memitem:ga34abd9ece8bad43b617ced6e018af08c"><td class="memItemLeft" align="right" valign="top">static uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__src.html#ga34abd9ece8bad43b617ced6e018af08c">SRC_GetBootModeWord1</a> (SRC_Type *base)</td></tr>
<tr class="memdesc:ga34abd9ece8bad43b617ced6e018af08c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the boot mode register 1 value.  <a href="#ga34abd9ece8bad43b617ced6e018af08c">More...</a><br/></td></tr>
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<tr class="memitem:gab850f1217901abfd78a35096a3b30d64"><td class="memItemLeft" align="right" valign="top">static uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__src.html#gab850f1217901abfd78a35096a3b30d64">SRC_GetBootModeWord2</a> (SRC_Type *base)</td></tr>
<tr class="memdesc:gab850f1217901abfd78a35096a3b30d64"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the boot mode register 2 value.  <a href="#gab850f1217901abfd78a35096a3b30d64">More...</a><br/></td></tr>
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<tr class="memitem:gae7bdfcb753a5abc9428de4c6169410b4"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__src.html#gae7bdfcb753a5abc9428de4c6169410b4">SRC_SetWarmBootIndication</a> (SRC_Type *base, bool enable)</td></tr>
<tr class="memdesc:gae7bdfcb753a5abc9428de4c6169410b4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the warm boot indication flag.  <a href="#gae7bdfcb753a5abc9428de4c6169410b4">More...</a><br/></td></tr>
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<tr class="memitem:gac15086ff9e2d490efc95b8a5577cbae6"><td class="memItemLeft" align="right" valign="top">static uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__src.html#gac15086ff9e2d490efc95b8a5577cbae6">SRC_GetResetStatusFlags</a> (SRC_Type *base)</td></tr>
<tr class="memdesc:gac15086ff9e2d490efc95b8a5577cbae6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the status flags of SRC.  <a href="#gac15086ff9e2d490efc95b8a5577cbae6">More...</a><br/></td></tr>
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<tr class="memitem:ga36d75f094528c8d5e37a77b4d45b617e"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__src.html#ga36d75f094528c8d5e37a77b4d45b617e">SRC_ClearResetStatusFlags</a> (SRC_Type *base, uint32_t flags)</td></tr>
<tr class="memdesc:ga36d75f094528c8d5e37a77b4d45b617e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clear the status flags of SRC.  <a href="#ga36d75f094528c8d5e37a77b4d45b617e">More...</a><br/></td></tr>
<tr class="separator:ga36d75f094528c8d5e37a77b4d45b617e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8c2062f093d4a0d164354ac7a2f4b3e2"><td class="memItemLeft" align="right" valign="top">static void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__src.html#ga8c2062f093d4a0d164354ac7a2f4b3e2">SRC_SetGeneralPurposeRegister</a> (SRC_Type *base, uint32_t index, uint32_t value)</td></tr>
<tr class="memdesc:ga8c2062f093d4a0d164354ac7a2f4b3e2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set value to general purpose registers.  <a href="#ga8c2062f093d4a0d164354ac7a2f4b3e2">More...</a><br/></td></tr>
<tr class="separator:ga8c2062f093d4a0d164354ac7a2f4b3e2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8c5e46dd8c4e1bd20aa737cfef532ab1"><td class="memItemLeft" align="right" valign="top">static uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__src.html#ga8c5e46dd8c4e1bd20aa737cfef532ab1">SRC_GetGeneralPurposeRegister</a> (SRC_Type *base, uint32_t index)</td></tr>
<tr class="memdesc:ga8c5e46dd8c4e1bd20aa737cfef532ab1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the value from general purpose registers.  <a href="#ga8c5e46dd8c4e1bd20aa737cfef532ab1">More...</a><br/></td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
Driver version</h2></td></tr>
<tr class="memitem:gab27a1d7efba9d270e93527f1d2c54605"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__src.html#gab27a1d7efba9d270e93527f1d2c54605">FSL_SRC_DRIVER_VERSION</a>&#160;&#160;&#160;(MAKE_VERSION(2, 0, 0))</td></tr>
<tr class="memdesc:gab27a1d7efba9d270e93527f1d2c54605"><td class="mdescLeft">&#160;</td><td class="mdescRight">SRC driver version 2.0.0.  <a href="#gab27a1d7efba9d270e93527f1d2c54605">More...</a><br/></td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="gab27a1d7efba9d270e93527f1d2c54605"></a>
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          <td class="memname">#define FSL_SRC_DRIVER_VERSION&#160;&#160;&#160;(MAKE_VERSION(2, 0, 0))</td>
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</div>
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<h2 class="groupheader">Enumeration Type Documentation</h2>
<a class="anchor" id="gaf647f7dbfbed8b1612675ab132cfa244"></a>
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          <td class="memname">enum <a class="el" href="group__src.html#gaf647f7dbfbed8b1612675ab132cfa244">_src_reset_status_flags</a></td>
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<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="ggaf647f7dbfbed8b1612675ab132cfa244a1ec8e8b05164a48af564b20d8a3f667a"></a>kSRC_WarmBootIndicationFlag</em>&nbsp;</td><td class="fielddoc">
<p>WARM boot indication shows that WARM boot was initiated by software. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="ggaf647f7dbfbed8b1612675ab132cfa244a35d666ccd943a593bc1af289e6233adb"></a>kSRC_TemperatureSensorResetFlag</em>&nbsp;</td><td class="fielddoc">
<p>Indicates whether the reset was the result of software reset from on-chip Temperature Sensor. </p>
<p>Temperature Sensor Interrupt need be served before this bit can be cleaned. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="ggaf647f7dbfbed8b1612675ab132cfa244a0cfd86a5b8b7110fac02e1304d33d218"></a>kSRC_Wdog3ResetFlag</em>&nbsp;</td><td class="fielddoc">
<p>IC Watchdog3 Time-out reset. </p>
<p>Indicates whether the reset was the result of the watchdog3 time-out event. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="ggaf647f7dbfbed8b1612675ab132cfa244abc557d5e2e199f9727744af4b181602b"></a>kSRC_JTAGSoftwareResetFlag</em>&nbsp;</td><td class="fielddoc">
<p>Indicates whether the reset was the result of setting SJC_GPCCR bit 31. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="ggaf647f7dbfbed8b1612675ab132cfa244a8a43d19a82614c4c1d571dad1f492628"></a>kSRC_JTAGGeneratedResetFlag</em>&nbsp;</td><td class="fielddoc">
<p>Indicates a reset has been caused by JTAG selection of certain IR codes: EXTEST or HIGHZ. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="ggaf647f7dbfbed8b1612675ab132cfa244abce52ce03031bdb1b0d76576daf418df"></a>kSRC_WatchdogResetFlag</em>&nbsp;</td><td class="fielddoc">
<p>Indicates a reset has been caused by the watchdog timer timing out. </p>
<p>This reset source can be blocked by disabling the watchdog. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="ggaf647f7dbfbed8b1612675ab132cfa244af8e87b67801dd22376d5b284722d02e3"></a>kSRC_IppUserResetFlag</em>&nbsp;</td><td class="fielddoc">
<p>Indicates whether the reset was the result of the ipp_user_reset_b qualified reset. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="ggaf647f7dbfbed8b1612675ab132cfa244a3008203f1efa3b9385545f53445844fb"></a>kSRC_CsuResetFlag</em>&nbsp;</td><td class="fielddoc">
<p>Indicates whether the reset was the result of the csu_reset_b input. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="ggaf647f7dbfbed8b1612675ab132cfa244af7eba139e63dffc69983a262551a8856"></a>kSRC_IppResetPinFlag</em>&nbsp;</td><td class="fielddoc">
<p>Indicates whether reset was the result of ipp_reset_b pin (Power-up sequence). </p>
</td></tr>
</table>

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          <td class="memname">enum <a class="el" href="group__src.html#ga95d1580a5ef39f6d3a5152a1be58e1ba">_src_status_flags</a></td>
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="gga95d1580a5ef39f6d3a5152a1be58e1baa53addfa0a919d77cdfa12c3c6114e88f"></a>kSRC_Core0WdogResetReqFlag</em>&nbsp;</td><td class="fielddoc">
<p>WDOG reset request from core0. </p>
<p>Read-only status bit. </p>
</td></tr>
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          <td class="memname">enum <a class="el" href="group__src.html#gac64aa4121e8d426a94f0826bbd7d49ac">src_mix_reset_stretch_cycles_t</a></td>
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<p>This type defines the SoC mix (Audio, ENET, uSDHC, EIM, QSPI, OCRAM, MMDC, etc) power up reset stretch mix reset width with the optional count of cycles </p>
<table class="fieldtable">
<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="ggac64aa4121e8d426a94f0826bbd7d49acaa217f0915ef6135677b3a91fc79331f0"></a>kSRC_MixResetStretchCycleAlt0</em>&nbsp;</td><td class="fielddoc">
<p>mix reset width is 1 x 88 ipg_cycle cycles. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="ggac64aa4121e8d426a94f0826bbd7d49aca08bea4f6078f98076d09164fb79a24fe"></a>kSRC_MixResetStretchCycleAlt1</em>&nbsp;</td><td class="fielddoc">
<p>mix reset width is 2 x 88 ipg_cycle cycles. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="ggac64aa4121e8d426a94f0826bbd7d49aca523d03fc789c467d88fe744cb4aafd44"></a>kSRC_MixResetStretchCycleAlt2</em>&nbsp;</td><td class="fielddoc">
<p>mix reset width is 3 x 88 ipg_cycle cycles. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="ggac64aa4121e8d426a94f0826bbd7d49acae0e765d1cd3898d811c441c5da436c9c"></a>kSRC_MixResetStretchCycleAlt3</em>&nbsp;</td><td class="fielddoc">
<p>mix reset width is 4 x 88 ipg_cycle cycles. </p>
</td></tr>
</table>

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<a class="anchor" id="ga24d2539758a32392b0d25f46a9f90b4e"></a>
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          <td class="memname">enum <a class="el" href="group__src.html#ga24d2539758a32392b0d25f46a9f90b4e">src_wdog3_reset_option_t</a></td>
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="gga24d2539758a32392b0d25f46a9f90b4eafb2fea029e1f79976dd556e130e2fbca"></a>kSRC_Wdog3ResetOptionAlt0</em>&nbsp;</td><td class="fielddoc">
<p>Wdog3_rst_b asserts M4 reset (default). </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="gga24d2539758a32392b0d25f46a9f90b4ea93e0c56b34582af6b2713feda778912e"></a>kSRC_Wdog3ResetOptionAlt1</em>&nbsp;</td><td class="fielddoc">
<p>Wdog3_rst_b asserts global reset. </p>
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          <td class="memname">enum <a class="el" href="group__src.html#ga5b40161d6cf7c90a651afd9047b6bedd">src_warm_reset_bypass_count_t</a></td>
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<p>This type defines the 32KHz clock cycles to count before bypassing the MMDC acknowledge for WARM reset. If the MMDC acknowledge is not asserted before this counter is elapsed, a COLD reset will be initiated. </p>
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<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="gga5b40161d6cf7c90a651afd9047b6beddae2e8afc71fab41ccbac78e6a8d69ff62"></a>kSRC_WarmResetWaitAlways</em>&nbsp;</td><td class="fielddoc">
<p>System will wait until MMDC acknowledge is asserted. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="gga5b40161d6cf7c90a651afd9047b6beddad20bc2e2d97c95046d65940f111e9584"></a>kSRC_WarmResetWaitClk16</em>&nbsp;</td><td class="fielddoc">
<p>Wait 16 32KHz clock cycles before switching the reset. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="gga5b40161d6cf7c90a651afd9047b6bedda8c3d2f6cd0c0f36da9a342e3c3eb77f8"></a>kSRC_WarmResetWaitClk32</em>&nbsp;</td><td class="fielddoc">
<p>Wait 32 32KHz clock cycles before switching the reset. </p>
</td></tr>
<tr><td class="fieldname"><em><a class="anchor" id="gga5b40161d6cf7c90a651afd9047b6bedda5bbedec3e30404b252af1b02af0042c0"></a>kSRC_WarmResetWaitClk64</em>&nbsp;</td><td class="fielddoc">
<p>Wait 64 32KHz clock cycles before switching the reset. </p>
</td></tr>
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<h2 class="groupheader">Function Documentation</h2>
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          <td class="memname">static void SRC_EnableWDOG3Reset </td>
          <td>(</td>
          <td class="paramtype">SRC_Type *&#160;</td>
          <td class="paramname"><em>base</em>, </td>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">bool&#160;</td>
          <td class="paramname"><em>enable</em>&#160;</td>
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          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>The WDOG3 reset is enabled by default.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">base</td><td>SRC peripheral base address. </td></tr>
    <tr><td class="paramname">enable</td><td>Enable the reset or not. </td></tr>
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          <td class="memname">static void SRC_SetMixResetStretchCycles </td>
          <td>(</td>
          <td class="paramtype">SRC_Type *&#160;</td>
          <td class="paramname"><em>base</em>, </td>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__src.html#gac64aa4121e8d426a94f0826bbd7d49ac">src_mix_reset_stretch_cycles_t</a>&#160;</td>
          <td class="paramname"><em>option</em>&#160;</td>
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          <td>)</td>
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<dl class="params"><dt>Parameters</dt><dd>
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    <tr><td class="paramname">base</td><td>SRC peripheral base address. </td></tr>
    <tr><td class="paramname">option</td><td>Setting option, see to <a class="el" href="group__src.html#gac64aa4121e8d426a94f0826bbd7d49ac" title="Selection of SoC mix power reset stretch. ">src_mix_reset_stretch_cycles_t</a>. </td></tr>
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          <td class="memname">static void SRC_EnableCoreDebugResetAfterPowerGate </td>
          <td>(</td>
          <td class="paramtype">SRC_Type *&#160;</td>
          <td class="paramname"><em>base</em>, </td>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">bool&#160;</td>
          <td class="paramname"><em>enable</em>&#160;</td>
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          <td></td>
          <td>)</td>
          <td></td><td></td>
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<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">base</td><td>SRC peripheral base address. </td></tr>
    <tr><td class="paramname">enable</td><td>Enable the reset or not. </td></tr>
  </table>
  </dd>
</dl>

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          <td class="memname">static void SRC_SetWdog3ResetOption </td>
          <td>(</td>
          <td class="paramtype">SRC_Type *&#160;</td>
          <td class="paramname"><em>base</em>, </td>
        </tr>
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          <td class="paramtype"><a class="el" href="group__src.html#ga24d2539758a32392b0d25f46a9f90b4e">src_wdog3_reset_option_t</a>&#160;</td>
          <td class="paramname"><em>option</em>&#160;</td>
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          <td>)</td>
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<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">base</td><td>SRC peripheral base address. </td></tr>
    <tr><td class="paramname">option</td><td>Setting option, see to <a class="el" href="group__src.html#ga24d2539758a32392b0d25f46a9f90b4e" title="Selection of WDOG3 reset option. ">src_wdog3_reset_option_t</a>. </td></tr>
  </table>
  </dd>
</dl>

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          <td class="memname">static void SRC_DoSoftwareResetARMCoreDebug </td>
          <td>(</td>
          <td class="paramtype">SRC_Type *&#160;</td>
          <td class="paramname"><em>base</em></td><td>)</td>
          <td></td>
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<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">base</td><td>SRC peripheral base address. </td></tr>
  </table>
  </dd>
</dl>

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          <td class="memname">static bool SRC_GetSoftwareResetARMCoreDebugDone </td>
          <td>(</td>
          <td class="paramtype">SRC_Type *&#160;</td>
          <td class="paramname"><em>base</em></td><td>)</td>
          <td></td>
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<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">base</td><td>SRC peripheral base address. </td></tr>
  </table>
  </dd>
</dl>

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          <td class="memname">static void SRC_DoSoftwareResetARMCore0 </td>
          <td>(</td>
          <td class="paramtype">SRC_Type *&#160;</td>
          <td class="paramname"><em>base</em></td><td>)</td>
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<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">base</td><td>SRC peripheral base address. </td></tr>
  </table>
  </dd>
</dl>

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          <td class="memname">static bool SRC_GetSoftwareResetARMCore0Done </td>
          <td>(</td>
          <td class="paramtype">SRC_Type *&#160;</td>
          <td class="paramname"><em>base</em></td><td>)</td>
          <td></td>
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<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">base</td><td>SRC peripheral base address. </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>If the reset is done. </dd></dl>

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          <td class="memname">static void SRC_AssertEIMReset </td>
          <td>(</td>
          <td class="paramtype">SRC_Type *&#160;</td>
          <td class="paramname"><em>base</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">bool&#160;</td>
          <td class="paramname"><em>enable</em>&#160;</td>
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          <td></td>
          <td>)</td>
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<p>EIM reset is needed in order to reconfigure the EIM chip select. The software reset bit must de-asserted since this is not self-refresh.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">base</td><td>SRC peripheral base address. </td></tr>
    <tr><td class="paramname">enable</td><td>Make the assertion or not. </td></tr>
  </table>
  </dd>
</dl>

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          <td class="memname">static void SRC_EnableWDOGReset </td>
          <td>(</td>
          <td class="paramtype">SRC_Type *&#160;</td>
          <td class="paramname"><em>base</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">bool&#160;</td>
          <td class="paramname"><em>enable</em>&#160;</td>
        </tr>
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          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>WDOG Reset is enabled in SRC by default. If the WDOG event to SRC is masked, it would not create a reset to the chip. During the time the WDOG event is masked, when the WDOG event flag is asserted, it would remain asserted regardless of servicing the WDOG module. The only way to clear that bit is the hardware reset.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">base</td><td>SRC peripheral base address. </td></tr>
    <tr><td class="paramname">enable</td><td>Enable the reset or not. </td></tr>
  </table>
  </dd>
</dl>

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          <td class="memname">static void SRC_SetWarmResetBypassCount </td>
          <td>(</td>
          <td class="paramtype">SRC_Type *&#160;</td>
          <td class="paramname"><em>base</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__src.html#ga5b40161d6cf7c90a651afd9047b6bedd">src_warm_reset_bypass_count_t</a>&#160;</td>
          <td class="paramname"><em>option</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>This function would define the 32KHz clock cycles to count before bypassing the MMDC acknowledge for WARM reset. If the MMDC acknowledge is not asserted before this counter is elapsed, a COLD reset will be initiated.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">base</td><td>SRC peripheral base address. </td></tr>
    <tr><td class="paramname">option</td><td>The option of setting mode, see to <a class="el" href="group__src.html#ga5b40161d6cf7c90a651afd9047b6bedd" title="Selection of WARM reset bypass count. ">src_warm_reset_bypass_count_t</a>. </td></tr>
  </table>
  </dd>
</dl>

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          <td class="memname">static void SRC_EnableWarmReset </td>
          <td>(</td>
          <td class="paramtype">SRC_Type *&#160;</td>
          <td class="paramname"><em>base</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">bool&#160;</td>
          <td class="paramname"><em>enable</em>&#160;</td>
        </tr>
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          <td></td>
          <td>)</td>
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<p>Only when the WARM reset is enabled, the WARM reset requests would be served by WARM reset. Otherwise, all the WARM reset sources would generate COLD reset.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">base</td><td>SRC peripheral base address. </td></tr>
    <tr><td class="paramname">enable</td><td>Enable the WARM reset or not. </td></tr>
  </table>
  </dd>
</dl>

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          <td class="memname">static uint32_t SRC_GetStatusFlags </td>
          <td>(</td>
          <td class="paramtype">SRC_Type *&#160;</td>
          <td class="paramname"><em>base</em></td><td>)</td>
          <td></td>
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<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">base</td><td>SRC peripheral base address. </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Mask value of status flags. See to $_src_status_flags. </dd></dl>

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          <td class="memname">static uint32_t SRC_GetBootModeWord1 </td>
          <td>(</td>
          <td class="paramtype">SRC_Type *&#160;</td>
          <td class="paramname"><em>base</em></td><td>)</td>
          <td></td>
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<p>The Boot Mode register contains bits that reflect the status of BOOT_CFGx pins of the chip. See to chip-specific document for detail information about value.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">base</td><td>SRC peripheral base address. </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>status of BOOT_CFGx pins of the chip. </dd></dl>

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          <td class="memname">static uint32_t SRC_GetBootModeWord2 </td>
          <td>(</td>
          <td class="paramtype">SRC_Type *&#160;</td>
          <td class="paramname"><em>base</em></td><td>)</td>
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<p>The Boot Mode register contains bits that reflect the status of BOOT_MODEx Pins and fuse values that controls boot of the chip. See to chip-specific document for detail information about value.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">base</td><td>SRC peripheral base address. </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>status of BOOT_MODEx Pins and fuse values that controls boot of the chip. </dd></dl>

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          <td class="memname">static void SRC_SetWarmBootIndication </td>
          <td>(</td>
          <td class="paramtype">SRC_Type *&#160;</td>
          <td class="paramname"><em>base</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">bool&#160;</td>
          <td class="paramname"><em>enable</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
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<p>WARM boot indication shows that WARM boot was initiated by software. This indicates to the software that it saved the needed information in the memory before initiating the WARM reset. In this case, software will set this bit to '1', before initiating the WARM reset. The warm_boot bit should be used as indication only after a warm_reset sequence. Software should clear this bit after warm_reset to indicate that the next warm_reset is not performed with warm_boot.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">base</td><td>SRC peripheral base address. </td></tr>
    <tr><td class="paramname">enable</td><td>Assert the flag or not. </td></tr>
  </table>
  </dd>
</dl>

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          <td class="memname">static uint32_t SRC_GetResetStatusFlags </td>
          <td>(</td>
          <td class="paramtype">SRC_Type *&#160;</td>
          <td class="paramname"><em>base</em></td><td>)</td>
          <td></td>
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<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">base</td><td>SRC peripheral base address. </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Mask value of status flags, see to <a class="el" href="group__src.html#gaf647f7dbfbed8b1612675ab132cfa244" title="SRC reset status flags. ">_src_reset_status_flags</a>. </dd></dl>

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          <td class="memname">void SRC_ClearResetStatusFlags </td>
          <td>(</td>
          <td class="paramtype">SRC_Type *&#160;</td>
          <td class="paramname"><em>base</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>flags</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
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<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">base</td><td>SRC peripheral base address. </td></tr>
    <tr><td class="paramname">Mask</td><td>value of status flags to be cleared, see to <a class="el" href="group__src.html#gaf647f7dbfbed8b1612675ab132cfa244" title="SRC reset status flags. ">_src_reset_status_flags</a>. </td></tr>
  </table>
  </dd>
</dl>

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          <td class="memname">static void SRC_SetGeneralPurposeRegister </td>
          <td>(</td>
          <td class="paramtype">SRC_Type *&#160;</td>
          <td class="paramname"><em>base</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>index</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>value</em>&#160;</td>
        </tr>
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          <td></td>
          <td>)</td>
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        </tr>
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<p>General purpose registers (GPRx) would hold the value during reset process. Wakeup function could be kept in these register. For example, the GPR1 holds the entry function for waking-up from Partial SLEEP mode while the GPR2 holds the argument. Other GPRx register would store the arbitray values.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">base</td><td>SRC peripheral base address. </td></tr>
    <tr><td class="paramname">index</td><td>The index of GPRx register array. Note index 0 reponses the GPR1 register. </td></tr>
    <tr><td class="paramname">value</td><td>Setting value for GPRx register. </td></tr>
  </table>
  </dd>
</dl>

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          <td class="memname">static uint32_t SRC_GetGeneralPurposeRegister </td>
          <td>(</td>
          <td class="paramtype">SRC_Type *&#160;</td>
          <td class="paramname"><em>base</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>index</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
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        </tr>
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<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">base</td><td>SRC peripheral base address. </td></tr>
    <tr><td class="paramname">index</td><td>The index of GPRx register array. Note index 0 reponses the GPR1 register. </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The setting value for GPRx register. </dd></dl>

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